Parallel Decoder for Low Density Parity Check Codes: A MPSoC Study

Sudeep Kanur Chandra Shekar; Georgios Georgakarakos; Antti Siirilä; Jérémie Lagravière; Kristian Nybom; Sebastien Lafond; Johan Lilius

doi:10.1109/HPCSim.2013.6641414

Parallel Decoder for Low Density Parity Check Codes: A MPSoC Study

Sudeep Kanur Chandra Shekar, Georgios Georgakarakos, Antti Siirilä, Jérémie Lagravière, Kristian Nybom, Sebastien Lafond, Johan Lilius

Information Technology

Research output: Chapter in Book/Conference proceeding › Conference contribution › Scientific › peer-review

Abstract

The near channel performance of Low Density Parity Check Codes (LDPC) has motivated its wide applications. Itera- tive decoding of LDPC codes provides significant implementation challenges as the complexity grows with the code size. Recent trends in integrating Multiprocessor System on Chip (MPSoC) with Network on Chip (NoC) gives a modular platform for parallel implementation. This paper presents an implementation platform for decoding LDPC codes based on HeMPS, an open source MPSoC framework based on NoC communication fabric. Reduced minimum sum algorithm is used for decoding LDPC codes and simulations are performed using HeMPS tool. The data rate and speedup factor measured for decoding a rate 1/2 LDPC code characterised by 252 × 504 parity matrix is presented.

Original language	Undefined/Unknown
Title of host publication	High Performance Computing and Simulation (HPCS), 2013 International Conference on
Editors	WW Smari, V Zeljkovic
Publisher	IEEE
Pages	202–206
ISBN (Print)	978-1-4799-0836-3
DOIs	https://doi.org/10.1109/HPCSim.2013.6641414
Publication status	Published - 2013
MoE publication type	A4 Article in a conference publication
Event	International Conference on High Performance Computing and Simulation (HPCS) - International Conference on High Performance Computing and Simulation (HPCS), 2013 Duration: 1 Jul 2013 → 5 Jul 2013

Conference

Conference	International Conference on High Performance Computing and Simulation (HPCS)
Period	01/07/13 → 05/07/13

Access to Document

10.1109/HPCSim.2013.6641414

Cite this

Kanur Chandra Shekar, S., Georgakarakos, G., Siirilä, A., Lagravière, J., Nybom, K., Lafond, S., & Lilius, J. (2013). Parallel Decoder for Low Density Parity Check Codes: A MPSoC Study. In WW. Smari, & V. Zeljkovic (Eds.), High Performance Computing and Simulation (HPCS), 2013 International Conference on (pp. 202–206). IEEE. https://doi.org/10.1109/HPCSim.2013.6641414

@inproceedings{596f374f60c249cbba62df8a6dbc549b,

title = "Parallel Decoder for Low Density Parity Check Codes: A MPSoC Study",

abstract = "The near channel performance of Low Density Parity Check Codes (LDPC) has motivated its wide applications. Itera- tive decoding of LDPC codes provides significant implementation challenges as the complexity grows with the code size. Recent trends in integrating Multiprocessor System on Chip (MPSoC) with Network on Chip (NoC) gives a modular platform for parallel implementation. This paper presents an implementation platform for decoding LDPC codes based on HeMPS, an open source MPSoC framework based on NoC communication fabric. Reduced minimum sum algorithm is used for decoding LDPC codes and simulations are performed using HeMPS tool. The data rate and speedup factor measured for decoding a rate 1/2 LDPC code characterised by 252 × 504 parity matrix is presented.",

author = "{Kanur Chandra Shekar}, Sudeep and Georgios Georgakarakos and Antti Siiril{\"a} and J{\'e}r{\'e}mie Lagravi{\`e}re and Kristian Nybom and Sebastien Lafond and Johan Lilius",

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doi = "10.1109/HPCSim.2013.6641414",

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booktitle = "High Performance Computing and Simulation (HPCS), 2013 International Conference on",

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note = "International Conference on High Performance Computing and Simulation (HPCS) ; Conference date: 01-07-2013 Through 05-07-2013",

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Kanur Chandra Shekar, S, Georgakarakos, G, Siirilä, A, Lagravière, J, Nybom, K , Lafond, S & Lilius, J 2013, Parallel Decoder for Low Density Parity Check Codes: A MPSoC Study. in WW Smari & V Zeljkovic (eds), High Performance Computing and Simulation (HPCS), 2013 International Conference on. IEEE, pp. 202–206, International Conference on High Performance Computing and Simulation (HPCS), 01/07/13. https://doi.org/10.1109/HPCSim.2013.6641414

Parallel Decoder for Low Density Parity Check Codes: A MPSoC Study. / Kanur Chandra Shekar, Sudeep; Georgakarakos, Georgios; Siirilä, Antti et al.
High Performance Computing and Simulation (HPCS), 2013 International Conference on. ed. / WW Smari; V Zeljkovic. IEEE, 2013. p. 202–206.

Research output: Chapter in Book/Conference proceeding › Conference contribution › Scientific › peer-review

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T1 - Parallel Decoder for Low Density Parity Check Codes: A MPSoC Study

AU - Kanur Chandra Shekar, Sudeep

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AU - Lafond, Sebastien

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N2 - The near channel performance of Low Density Parity Check Codes (LDPC) has motivated its wide applications. Itera- tive decoding of LDPC codes provides significant implementation challenges as the complexity grows with the code size. Recent trends in integrating Multiprocessor System on Chip (MPSoC) with Network on Chip (NoC) gives a modular platform for parallel implementation. This paper presents an implementation platform for decoding LDPC codes based on HeMPS, an open source MPSoC framework based on NoC communication fabric. Reduced minimum sum algorithm is used for decoding LDPC codes and simulations are performed using HeMPS tool. The data rate and speedup factor measured for decoding a rate 1/2 LDPC code characterised by 252 × 504 parity matrix is presented.

AB - The near channel performance of Low Density Parity Check Codes (LDPC) has motivated its wide applications. Itera- tive decoding of LDPC codes provides significant implementation challenges as the complexity grows with the code size. Recent trends in integrating Multiprocessor System on Chip (MPSoC) with Network on Chip (NoC) gives a modular platform for parallel implementation. This paper presents an implementation platform for decoding LDPC codes based on HeMPS, an open source MPSoC framework based on NoC communication fabric. Reduced minimum sum algorithm is used for decoding LDPC codes and simulations are performed using HeMPS tool. The data rate and speedup factor measured for decoding a rate 1/2 LDPC code characterised by 252 × 504 parity matrix is presented.

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