Parallel Decoder for Low Density Parity Check Codes: A MPSoC Study

Research output: Chapter in Book/Conference proceedingConference contributionScientificpeer-review

Abstract

The near channel performance of Low Density Parity Check Codes (LDPC) has motivated its wide applications. Itera- tive decoding of LDPC codes provides significant implementation challenges as the complexity grows with the code size. Recent trends in integrating Multiprocessor System on Chip (MPSoC) with Network on Chip (NoC) gives a modular platform for parallel implementation. This paper presents an implementation platform for decoding LDPC codes based on HeMPS, an open source MPSoC framework based on NoC communication fabric. Reduced minimum sum algorithm is used for decoding LDPC codes and simulations are performed using HeMPS tool. The data rate and speedup factor measured for decoding a rate 1/2 LDPC code characterised by 252 × 504 parity matrix is presented.
Original languageUndefined/Unknown
Title of host publicationHigh Performance Computing and Simulation (HPCS), 2013 International Conference on
EditorsWW Smari, V Zeljkovic
PublisherIEEE
Pages202–206
ISBN (Print)978-1-4799-0836-3
DOIs
Publication statusPublished - 2013
MoE publication typeA4 Article in a conference publication
EventInternational Conference on High Performance Computing and Simulation (HPCS) - International Conference on High Performance Computing and Simulation (HPCS), 2013
Duration: 1 Jul 20135 Jul 2013

Conference

ConferenceInternational Conference on High Performance Computing and Simulation (HPCS)
Period01/07/1305/07/13

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