Parallel Decoder for Low Density Parity Check Codes: A MPSoC Study

Tutkimustuotos: Artikkeli kirjassa/raportissa/konferenssijulkaisussaKonferenssiartikkeliTieteellinenvertaisarvioitu

Abstrakti

The near channel performance of Low Density Parity Check Codes (LDPC) has motivated its wide applications. Itera- tive decoding of LDPC codes provides significant implementation challenges as the complexity grows with the code size. Recent trends in integrating Multiprocessor System on Chip (MPSoC) with Network on Chip (NoC) gives a modular platform for parallel implementation. This paper presents an implementation platform for decoding LDPC codes based on HeMPS, an open source MPSoC framework based on NoC communication fabric. Reduced minimum sum algorithm is used for decoding LDPC codes and simulations are performed using HeMPS tool. The data rate and speedup factor measured for decoding a rate 1/2 LDPC code characterised by 252 × 504 parity matrix is presented.
AlkuperäiskieliEi tiedossa
OtsikkoHigh Performance Computing and Simulation (HPCS), 2013 International Conference on
ToimittajatWW Smari, V Zeljkovic
KustantajaIEEE
Sivut202–206
ISBN (painettu)978-1-4799-0836-3
DOI - pysyväislinkit
TilaJulkaistu - 2013
OKM-julkaisutyyppiA4 Artikkeli konferenssijulkaisuussa
TapahtumaInternational Conference on High Performance Computing and Simulation (HPCS) - International Conference on High Performance Computing and Simulation (HPCS), 2013
Kesto: 1 heinäkuuta 20135 heinäkuuta 2013

Konferenssi

KonferenssiInternational Conference on High Performance Computing and Simulation (HPCS)
Ajanjakso01/07/1305/07/13

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