Parallel Decoder for Low Density Parity Check Codes: A MPSoC Study

Sudeep Kanur Chandra Shekar; Georgios Georgakarakos; Antti Siirilä; Jérémie Lagravière; Kristian Nybom; Sebastien Lafond; Johan Lilius

doi:10.1109/HPCSim.2013.6641414

Parallel Decoder for Low Density Parity Check Codes: A MPSoC Study

Sudeep Kanur Chandra Shekar, Georgios Georgakarakos, Antti Siirilä, Jérémie Lagravière, Kristian Nybom, Sebastien Lafond, Johan Lilius

Informaatioteknologia

Tutkimustuotos: Artikkeli kirjassa/raportissa/konferenssijulkaisussa › Konferenssiartikkeli › Tieteellinen › vertaisarvioitu

Abstrakti

The near channel performance of Low Density Parity Check Codes (LDPC) has motivated its wide applications. Itera- tive decoding of LDPC codes provides significant implementation challenges as the complexity grows with the code size. Recent trends in integrating Multiprocessor System on Chip (MPSoC) with Network on Chip (NoC) gives a modular platform for parallel implementation. This paper presents an implementation platform for decoding LDPC codes based on HeMPS, an open source MPSoC framework based on NoC communication fabric. Reduced minimum sum algorithm is used for decoding LDPC codes and simulations are performed using HeMPS tool. The data rate and speedup factor measured for decoding a rate 1/2 LDPC code characterised by 252 × 504 parity matrix is presented.

Alkuperäiskieli	Ei tiedossa
Otsikko	High Performance Computing and Simulation (HPCS), 2013 International Conference on
Toimittajat	WW Smari, V Zeljkovic
Kustantaja	IEEE
Sivut	202–206
ISBN (painettu)	978-1-4799-0836-3
DOI - pysyväislinkit	https://doi.org/10.1109/HPCSim.2013.6641414
Tila	Julkaistu - 2013
OKM-julkaisutyyppi	A4 Artikkeli konferenssijulkaisuussa
Tapahtuma	International Conference on High Performance Computing and Simulation (HPCS) - International Conference on High Performance Computing and Simulation (HPCS), 2013 Kesto: 1 heinäk. 2013 → 5 heinäk. 2013

Konferenssi

Konferenssi	International Conference on High Performance Computing and Simulation (HPCS)
Ajanjakso	01/07/13 → 05/07/13

Pääsy asiakirjaan

10.1109/HPCSim.2013.6641414

Viittausmuodot

Kanur Chandra Shekar, S., Georgakarakos, G., Siirilä, A., Lagravière, J., Nybom, K., Lafond, S., & Lilius, J. (2013). Parallel Decoder for Low Density Parity Check Codes: A MPSoC Study. teoksessa WW. Smari, & V. Zeljkovic (Toimittajat), High Performance Computing and Simulation (HPCS), 2013 International Conference on (Sivut 202–206). IEEE. https://doi.org/10.1109/HPCSim.2013.6641414

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title = "Parallel Decoder for Low Density Parity Check Codes: A MPSoC Study",

abstract = "The near channel performance of Low Density Parity Check Codes (LDPC) has motivated its wide applications. Itera- tive decoding of LDPC codes provides significant implementation challenges as the complexity grows with the code size. Recent trends in integrating Multiprocessor System on Chip (MPSoC) with Network on Chip (NoC) gives a modular platform for parallel implementation. This paper presents an implementation platform for decoding LDPC codes based on HeMPS, an open source MPSoC framework based on NoC communication fabric. Reduced minimum sum algorithm is used for decoding LDPC codes and simulations are performed using HeMPS tool. The data rate and speedup factor measured for decoding a rate 1/2 LDPC code characterised by 252 × 504 parity matrix is presented.",

author = "{Kanur Chandra Shekar}, Sudeep and Georgios Georgakarakos and Antti Siiril{\"a} and J{\'e}r{\'e}mie Lagravi{\`e}re and Kristian Nybom and Sebastien Lafond and Johan Lilius",

year = "2013",

doi = "10.1109/HPCSim.2013.6641414",

language = "Odefinierat/ok{\"a}nt",

isbn = "978-1-4799-0836-3",

pages = "202–206",

editor = "WW Smari and V Zeljkovic",

booktitle = "High Performance Computing and Simulation (HPCS), 2013 International Conference on",

publisher = "IEEE",

note = "International Conference on High Performance Computing and Simulation (HPCS) ; Conference date: 01-07-2013 Through 05-07-2013",

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Kanur Chandra Shekar, S, Georgakarakos, G, Siirilä, A, Lagravière, J, Nybom, K , Lafond, S & Lilius, J 2013, Parallel Decoder for Low Density Parity Check Codes: A MPSoC Study. julkaisussa WW Smari & V Zeljkovic (toim), High Performance Computing and Simulation (HPCS), 2013 International Conference on. IEEE, Sivut 202–206, International Conference on High Performance Computing and Simulation (HPCS), 01/07/13. https://doi.org/10.1109/HPCSim.2013.6641414

Parallel Decoder for Low Density Parity Check Codes: A MPSoC Study. / Kanur Chandra Shekar, Sudeep; Georgakarakos, Georgios; Siirilä, Antti et al.
High Performance Computing and Simulation (HPCS), 2013 International Conference on. toim. / WW Smari; V Zeljkovic. IEEE, 2013. s. 202–206.

Tutkimustuotos: Artikkeli kirjassa/raportissa/konferenssijulkaisussa › Konferenssiartikkeli › Tieteellinen › vertaisarvioitu

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T1 - Parallel Decoder for Low Density Parity Check Codes: A MPSoC Study

AU - Kanur Chandra Shekar, Sudeep

AU - Georgakarakos, Georgios

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AU - Lagravière, Jérémie

AU - Nybom, Kristian

AU - Lafond, Sebastien

AU - Lilius, Johan

PY - 2013

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N2 - The near channel performance of Low Density Parity Check Codes (LDPC) has motivated its wide applications. Itera- tive decoding of LDPC codes provides significant implementation challenges as the complexity grows with the code size. Recent trends in integrating Multiprocessor System on Chip (MPSoC) with Network on Chip (NoC) gives a modular platform for parallel implementation. This paper presents an implementation platform for decoding LDPC codes based on HeMPS, an open source MPSoC framework based on NoC communication fabric. Reduced minimum sum algorithm is used for decoding LDPC codes and simulations are performed using HeMPS tool. The data rate and speedup factor measured for decoding a rate 1/2 LDPC code characterised by 252 × 504 parity matrix is presented.

AB - The near channel performance of Low Density Parity Check Codes (LDPC) has motivated its wide applications. Itera- tive decoding of LDPC codes provides significant implementation challenges as the complexity grows with the code size. Recent trends in integrating Multiprocessor System on Chip (MPSoC) with Network on Chip (NoC) gives a modular platform for parallel implementation. This paper presents an implementation platform for decoding LDPC codes based on HeMPS, an open source MPSoC framework based on NoC communication fabric. Reduced minimum sum algorithm is used for decoding LDPC codes and simulations are performed using HeMPS tool. The data rate and speedup factor measured for decoding a rate 1/2 LDPC code characterised by 252 × 504 parity matrix is presented.

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DO - 10.1109/HPCSim.2013.6641414

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BT - High Performance Computing and Simulation (HPCS), 2013 International Conference on

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