Interrupt costs in embedded system with short latency hardware accelerators

Sebastien Lafond; Johan Lilius

doi:10.1109/ECBS.2008.39

Interrupt costs in embedded system with short latency hardware accelerators

Sebastien Lafond, Johan Lilius

Forskningsoutput: Kapitel i bok/konferenshandling › Konferensbidrag › Vetenskaplig › Peer review

7 Citeringar (Scopus)

Sammanfattning

This paper presents a methodology for analyzing the impact of short latency hardware accelerators on a typical embedded system. We show that hardware accelerator granularity has a direct effect on the system performance in terms of cache misses, execution time and thus energy consumption.

Originalspråk	Odefinierat/okänt
Titel på värdpublikation	15th Annual IEEE International Conference and Workshop on the Engineering of Computer Based Systems, Proceedings
Redaktörer	Bustard, W. David, Sterritt, Roy
Förlag	International conference and workshops on engineering of computer-based systems
Sidor	317–325
Antal sidor	9
ISBN (tryckt)	978-0-7695-3141-0
DOI	https://doi.org/10.1109/ECBS.2008.39
Status	Publicerad - 2008
MoE-publikationstyp	A4 Artikel i en konferenspublikation
Evenemang	conference - Varaktighet: 1 jan. 2010 → …

Konferens

Konferens	conference
Period	01/01/10 → …

Åtkomst av dokument

10.1109/ECBS.2008.39

Citera det här

Lafond, S., & Lilius, J. (2008). Interrupt costs in embedded system with short latency hardware accelerators. I Bustard, W. David, Sterritt, & Roy (Red.), 15th Annual IEEE International Conference and Workshop on the Engineering of Computer Based Systems, Proceedings (s. 317–325). International conference and workshops on engineering of computer-based systems. https://doi.org/10.1109/ECBS.2008.39

Lafond, Sebastien ; Lilius, Johan. / Interrupt costs in embedded system with short latency hardware accelerators. 15th Annual IEEE International Conference and Workshop on the Engineering of Computer Based Systems, Proceedings. redaktör / Bustard ; W. David ; Sterritt ; Roy. International conference and workshops on engineering of computer-based systems, 2008. s. 317–325

@inproceedings{dabcb8ec1deb417f91d3e2e6b690a7ae,

title = "Interrupt costs in embedded system with short latency hardware accelerators",

abstract = "This paper presents a methodology for analyzing the impact of short latency hardware accelerators on a typical embedded system. We show that hardware accelerator granularity has a direct effect on the system performance in terms of cache misses, execution time and thus energy consumption.",

author = "Sebastien Lafond and Johan Lilius",

year = "2008",

doi = "10.1109/ECBS.2008.39",

language = "Odefinierat/ok{\"a}nt",

isbn = "978-0-7695-3141-0",

pages = "317–325",

editor = "Bustard and W. David and Sterritt and Roy",

booktitle = "15th Annual IEEE International Conference and Workshop on the Engineering of Computer Based Systems, Proceedings",

publisher = "International conference and workshops on engineering of computer-based systems",

note = "conference ; Conference date: 01-01-2010",

}

Lafond, S & Lilius, J 2008, Interrupt costs in embedded system with short latency hardware accelerators. i Bustard, W David, Sterritt & Roy (red), 15th Annual IEEE International Conference and Workshop on the Engineering of Computer Based Systems, Proceedings. International conference and workshops on engineering of computer-based systems, s. 317–325, conference, 01/01/10. https://doi.org/10.1109/ECBS.2008.39

Interrupt costs in embedded system with short latency hardware accelerators. / Lafond, Sebastien ; Lilius, Johan.
15th Annual IEEE International Conference and Workshop on the Engineering of Computer Based Systems, Proceedings. red. / Bustard; W. David; Sterritt; Roy. International conference and workshops on engineering of computer-based systems, 2008. s. 317–325.

Forskningsoutput: Kapitel i bok/konferenshandling › Konferensbidrag › Vetenskaplig › Peer review

TY - GEN

T1 - Interrupt costs in embedded system with short latency hardware accelerators

AU - Lafond, Sebastien

AU - Lilius, Johan

PY - 2008

Y1 - 2008

N2 - This paper presents a methodology for analyzing the impact of short latency hardware accelerators on a typical embedded system. We show that hardware accelerator granularity has a direct effect on the system performance in terms of cache misses, execution time and thus energy consumption.

AB - This paper presents a methodology for analyzing the impact of short latency hardware accelerators on a typical embedded system. We show that hardware accelerator granularity has a direct effect on the system performance in terms of cache misses, execution time and thus energy consumption.

U2 - 10.1109/ECBS.2008.39

DO - 10.1109/ECBS.2008.39

M3 - Konferensbidrag

SN - 978-0-7695-3141-0

SP - 317

EP - 325

BT - 15th Annual IEEE International Conference and Workshop on the Engineering of Computer Based Systems, Proceedings

A2 - Bustard, null

A2 - David, W.

A2 - Sterritt, null

A2 - Roy, null

PB - International conference and workshops on engineering of computer-based systems

T2 - conference

Y2 - 1 January 2010

ER -

Lafond S , Lilius J. Interrupt costs in embedded system with short latency hardware accelerators. I Bustard, David W, Sterritt, Roy, redaktörer, 15th Annual IEEE International Conference and Workshop on the Engineering of Computer Based Systems, Proceedings. International conference and workshops on engineering of computer-based systems. 2008. s. 317–325 doi: 10.1109/ECBS.2008.39