Energy budget is becoming a constraint in all computing systems. From mobile systems to supercomputers, the focus has shifted from performance to energy and power efficiency. Design metrics are not anymore solely based on performance, as the energy efficiency of application executions is becoming a predominant design requirement. In addition to established voltage and frequency scaling techniques, several semiconductor chip manufactures introduced heterogeneous multi-core processors to increase the level of energy efficiency. The usage of this heterogeneity is complicated by the scheduling and mapping decisions needed to be made at run-time for application execution. In order to exploit the full potential of such architectures we need to make the right decisions, because parameters such as type of core, frequency and utilization usually affect the power dissipation and performance. This paper analyses achievable energy gains when exploiting core level utilization in addition to other control techniques such as: heterogeneity, voltage and frequency scaling. We build an energy efficiency model based on platform configurations defined by core types, the different voltage and frequency levels and the core utilization rate. Based on the built model, we analyze the energy efficiency variations for different platform configurations providing the same level of performance. We show that trading the number and type of core with frequency and voltage level and core utilization rate can lead to substantial energy efficiency gains.
|Titel på gästpublikation||Parallel, Distributed and Network-based Processing (PDP), 2017 25th Euromicro International Conference on|
|Status||Publicerad - 2017|
|MoE-publikationstyp||A4 Artikel i en konferenspublikation|
|Evenemang||Euromicro International Conference on Parallel, Distributed and Network-based Processing - |
Varaktighet: 6 mar 2017 → 8 mar 2017
|Konferens||Euromicro International Conference on Parallel, Distributed and Network-based Processing|
|Period||06/03/17 → 08/03/17|