Accelerating Viterbi Algorithm using Custom Instruction Approach

Waqar Ahmed, Imran Hafeez Abbassi, Muhammad Usman Sanwal, Hasan Mahmood

    Forskningsoutput: Kapitel i bok/konferenshandlingKonferensbidragVetenskapligPeer review

    Sammanfattning

    In recent years, the decoding algorithms in communication networks are becoming increasingly complex aiming to achieve high reliability in correctly decoding received messages. These decoding algorithms involve computationally complex operations requiring high performance computing hardware, which are generally expensive. A cost-effective solution is to enhance the Instruction Set Architecture (ISA) of the processors by creating new custom instructions for the computational parts of the decoding algorithms. In this paper, we propose to utilize the custom instruction approach to efficiently implement the widely used Viterbi decoding algorithm by adding the assembly language instructions to the ISA of DLX, PicoJava II and NIOS II processors, which represent RISC, stack and FPGA-based soft-core processor architectures, respectively. By using the custom instruction approach, the execution time of the Viterbi algorithm is significantly improved by approximately 3 times for DLX and PicoJava II, and by 2 times for NIOS II.

    OriginalspråkOdefinierat/okänt
    Titel på gästpublikation2018 14th IEEE/ASME International Conference on Mechatronic and Embedded Systems and Applications (MESA)
    FörlagIEEE
    Sidor
    ISBN (tryckt)978-1-5386-4643-4
    DOI
    StatusPublicerad - 2018
    MoE-publikationstypA4 Artikel i en konferenspublikation
    EvenemangInternational Conference on Mechatronic and Embedded Systems and Applications (MESA) - 2018 14th IEEE/ASME International Conference on Mechatronic and Embedded Systems and Applications (MESA)
    Varaktighet: 2 jul 20184 jul 2018

    Konferens

    KonferensInternational Conference on Mechatronic and Embedded Systems and Applications (MESA)
    Period02/07/1804/07/18

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