Quantifying the Interaction Between Structural Properties of Software and Hardware in the ARM Big.LITTLE Architecture

Srboljub Stepanovic, Georgios Georgakarakos, Simon Holmbacka, Johan Lilius

Tutkimustuotos: Artikkeli kirjassa/raportissa/konferenssijulkaisussaKonferenssiartikkeliTieteellinenvertaisarvioitu

1 Sitaatiot (Scopus)
7 Lataukset (Pure)

Abstrakti

Heterogeneous architectures offer the opportunity to achieve high performance and energy efficiency by selecting appropriate cores for execution of ever changing software applications. Appropriate core selection depends on the interaction between the structural properties of the software and the hardware that influences performance of the software. We propose a model for efficient core selection when executing software on ARM's big.LITTLE heterogeneous architecture. It features a metric based on the correlation between the performance and the number of last level data cache (LLC) misses on a big and a LITTLE core. Additionally our model defines a soft threshold in terms of the number of LLC misses that determines efficient core selection. We verify the model on both a stress benchmark (stress-ng) and a performance and energy demanding application (HEVC decoding) using XMEM and Linux perf dynamic tools.
AlkuperäiskieliEi tiedossa
Otsikko2018 26th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP)
ToimittajatIvan Merelli, Pietro Lio, Igor Kotenko
KustantajaIEEE
Sivut138–144
ISBN (elektroninen)978-1-5386-4975-6
ISBN (painettu)978-1-5386-4976-3
DOI - pysyväislinkit
TilaJulkaistu - 2018
OKM-julkaisutyyppiA4 Artikkeli konferenssijulkaisuussa
TapahtumaEuromicro International Conference on Parallel, Distributed and Network-based Processing (PDP) - Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP)
Kesto: 21 maaliskuuta 201823 maaliskuuta 2018

Konferenssi

KonferenssiEuromicro International Conference on Parallel, Distributed and Network-based Processing (PDP)
Ajanjakso21/03/1823/03/18

Keywords

  • ARM big.LITTLE architecture
  • Benchmark testing
  • Cache storage
  • HEVC
  • Hardware
  • LITTLE heterogeneous architecture
  • LLC
  • Linux
  • Linux perf dynamic tools
  • Microarchitecture
  • Multicore processing
  • Performance evaluation
  • Pipelines
  • Shared memory systems
  • Software
  • Structural properties
  • Tools
  • XMEM
  • appropriate core selection
  • big.LITTLE
  • cycles per instruction
  • efficient core selection
  • energy demanding application
  • executing software
  • heterogeneous architecture
  • heterogeneous architectures
  • high performance
  • last level data cache misses
  • microprocessor chips
  • multiprocessing systems
  • parallel architectures
  • power aware computing
  • soft threshold
  • software applications
  • stress-ng

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