Interrupt costs in embedded system with short latency hardware accelerators

Sebastien Lafond; Johan Lilius

doi:10.1109/ECBS.2008.39

Interrupt costs in embedded system with short latency hardware accelerators

Tutkimustuotos: Artikkeli kirjassa/raportissa/konferenssijulkaisussa › Konferenssiartikkeli › Tieteellinen › vertaisarvioitu

7 Sitaatiot (Scopus)

Abstrakti

This paper presents a methodology for analyzing the impact of short latency hardware accelerators on a typical embedded system. We show that hardware accelerator granularity has a direct effect on the system performance in terms of cache misses, execution time and thus energy consumption.

Alkuperäiskieli	Ei tiedossa
Otsikko	15th Annual IEEE International Conference and Workshop on the Engineering of Computer Based Systems, Proceedings
Toimittajat	Bustard, W. David, Sterritt, Roy
Kustantaja	International conference and workshops on engineering of computer-based systems
Sivut	317–325
Sivumäärä	9
ISBN (painettu)	978-0-7695-3141-0
DOI - pysyväislinkit	https://doi.org/10.1109/ECBS.2008.39
Tila	Julkaistu - 2008
OKM-julkaisutyyppi	A4 Artikkeli konferenssijulkaisuussa
Tapahtuma	conference - Kesto: 1 tammik. 2010 → …

Konferenssi

Konferenssi	conference
Ajanjakso	01/01/10 → …

Pääsy asiakirjaan

10.1109/ECBS.2008.39

Viittausmuodot

Lafond, S., & Lilius, J. (2008). Interrupt costs in embedded system with short latency hardware accelerators. teoksessa Bustard, W. David, Sterritt, & Roy (Toimittajat), 15th Annual IEEE International Conference and Workshop on the Engineering of Computer Based Systems, Proceedings (Sivut 317–325). International conference and workshops on engineering of computer-based systems. https://doi.org/10.1109/ECBS.2008.39

Lafond, Sebastien ; Lilius, Johan. / Interrupt costs in embedded system with short latency hardware accelerators. 15th Annual IEEE International Conference and Workshop on the Engineering of Computer Based Systems, Proceedings. Toimittaja / Bustard ; W. David ; Sterritt ; Roy. International conference and workshops on engineering of computer-based systems, 2008. Sivut 317–325

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abstract = "This paper presents a methodology for analyzing the impact of short latency hardware accelerators on a typical embedded system. We show that hardware accelerator granularity has a direct effect on the system performance in terms of cache misses, execution time and thus energy consumption.",

author = "Sebastien Lafond and Johan Lilius",

year = "2008",

doi = "10.1109/ECBS.2008.39",

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Lafond, S & Lilius, J 2008, Interrupt costs in embedded system with short latency hardware accelerators. julkaisussa Bustard, W David, Sterritt & Roy (toim), 15th Annual IEEE International Conference and Workshop on the Engineering of Computer Based Systems, Proceedings. International conference and workshops on engineering of computer-based systems, Sivut 317–325, conference, 01/01/10. https://doi.org/10.1109/ECBS.2008.39

Interrupt costs in embedded system with short latency hardware accelerators. / Lafond, Sebastien ; Lilius, Johan.
15th Annual IEEE International Conference and Workshop on the Engineering of Computer Based Systems, Proceedings. toim. / Bustard; W. David; Sterritt; Roy. International conference and workshops on engineering of computer-based systems, 2008. s. 317–325.

Tutkimustuotos: Artikkeli kirjassa/raportissa/konferenssijulkaisussa › Konferenssiartikkeli › Tieteellinen › vertaisarvioitu

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AU - Lafond, Sebastien

AU - Lilius, Johan

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N2 - This paper presents a methodology for analyzing the impact of short latency hardware accelerators on a typical embedded system. We show that hardware accelerator granularity has a direct effect on the system performance in terms of cache misses, execution time and thus energy consumption.

AB - This paper presents a methodology for analyzing the impact of short latency hardware accelerators on a typical embedded system. We show that hardware accelerator granularity has a direct effect on the system performance in terms of cache misses, execution time and thus energy consumption.

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DO - 10.1109/ECBS.2008.39

M3 - Publicerad konferensartikel

SN - 978-0-7695-3141-0

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BT - 15th Annual IEEE International Conference and Workshop on the Engineering of Computer Based Systems, Proceedings

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Lafond S , Lilius J. Interrupt costs in embedded system with short latency hardware accelerators. julkaisussa Bustard, David W, Sterritt, Roy, toimittajat, 15th Annual IEEE International Conference and Workshop on the Engineering of Computer Based Systems, Proceedings. International conference and workshops on engineering of computer-based systems. 2008. s. 317–325 doi: 10.1109/ECBS.2008.39