Thermal modelling of 3D multicore systems in a flip-chip package

Kameswar Rao Vaddina, Tamoghna Mitra, Pasi Liljeberg, Juha Plosila

    Research output: Chapter in Book/Conference proceedingConference contributionScientificpeer-review

    4 Citations (Scopus)

    Abstract

    Three-dimensional (3D) technology offers greater device integration, reduced signal delay and reduced interconnect power. It also provides greater design flexibility by allowing heterogeneous integration. In this work, a 3D thermal model of a multicore system is developed to investigate the effects of hotspot, and placement of silicon die layers, on the thermal performance of a modern flip-chip package. In this regard, both the steady-state and transient heat transfer analysis has been performed on the 3D flip-chip package. Two different thermal models were evaluated under different operating conditions. Through experimental simulations, we have found a model which has better thermal performance. The optimal placement solution is also provided based on the maximum temperature attained by the individual silicon dies. We have also provided the improvement that is required in the heat sink thermal resistance of a 3D system when compared to the single-die system.
    Original languageUndefined/Unknown
    Title of host publicationSOC Conference (SOCC), 2010 IEEE International
    EditorsThomas Büchner
    PublisherIEEE
    Pages379–383
    ISBN (Print)978-1-4244-6682-5
    DOIs
    Publication statusPublished - 2010
    MoE publication typeA4 Article in a conference publication
    EventIEEE International SOC Conference - Las Vegas, NV
    Duration: 27 Sep 201029 Sep 2010

    Conference

    ConferenceIEEE International SOC Conference
    Period27/09/1029/09/10

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