Three-dimensional (3D) technology offers greater device integration, reduced signal delay and reduced interconnect power. It also provides greater design flexibility by allowing heterogeneous integration. In this work, a 3D thermal model of a multicore system is developed to investigate the effects of hotspot, and placement of silicon die layers, on the thermal performance of a modern flip-chip package. In this regard, both the steady-state and transient heat transfer analysis has been performed on the 3D flip-chip package. Two different thermal models were evaluated under different operating conditions. Through experimental simulations, we have found a model which has better thermal performance. The optimal placement solution is also provided based on the maximum temperature attained by the individual silicon dies. We have also provided the improvement that is required in the heat sink thermal resistance of a 3D system when compared to the single-die system.
|Title of host publication||SOC Conference (SOCC), 2010 IEEE International|
|Publication status||Published - 2010|
|MoE publication type||A4 Article in a conference publication|
|Event||IEEE International SOC Conference - Las Vegas, NV|
Duration: 27 Sep 2010 → 29 Sep 2010
|Conference||IEEE International SOC Conference|
|Period||27/09/10 → 29/09/10|