Dataflow models of computation have early on been acknowledged as an attractive methodology to describe parallel algorithms, hence they have become highly relevant for programming in the current multicore processor era. While several frameworks provide tools to create dataflow descriptions of algorithms, generating parallel code for programmable processors is still sub-optimal due to the scheduling overheads and the semantics gap when expressing parallelism with conventional programming languages featuring threads. In this paper we propose an optimization of the parallel code generation process by combining dataflow and task programming models. We develop a task-based code generator for PREESM, a dataflow-based prototyping framework, in order to deploy algorithms described as synchronous dataflow graphs on multicore platforms. Experimental performance comparison of our task generated code against typical thread-based code shows that our approach removes significant scheduling and synchronization overheads while maintaining similar (and occasionally improving) application throughput.
|Title of host publication||Signal Processing Systems (SiPS), 2017 IEEE International Workshop on|
|Publication status||Published - 2017|
|MoE publication type||A4 Article in a conference publication|
|Event||IEEE International Workshop on Signal Processing Systems (SiPS) - IEEE International Workshop on Signal Processing Systems (SiPS), 2017|
Duration: 3 Oct 2017 → 5 Oct 2017
|Conference||IEEE International Workshop on Signal Processing Systems (SiPS)|
|Period||03/10/17 → 05/10/17|