Interrupt costs in embedded system with short latency hardware accelerators

Sebastien Lafond; Johan Lilius

doi:10.1109/ECBS.2008.39

Interrupt costs in embedded system with short latency hardware accelerators

Research output: Chapter in Book/Conference proceeding › Published conference proceeding › Scientific › peer-review

7 Citations (Scopus)

Abstract

This paper presents a methodology for analyzing the impact of short latency hardware accelerators on a typical embedded system. We show that hardware accelerator granularity has a direct effect on the system performance in terms of cache misses, execution time and thus energy consumption.

Original language	Undefined/Unknown
Title of host publication	15th Annual IEEE International Conference and Workshop on the Engineering of Computer Based Systems, Proceedings
Editors	Bustard, W. David, Sterritt, Roy
Publisher	International conference and workshops on engineering of computer-based systems
Pages	317–325
Number of pages	9
ISBN (Print)	978-0-7695-3141-0
DOIs	https://doi.org/10.1109/ECBS.2008.39
Publication status	Published - 2008
MoE publication type	A4 Article in a conference publication
Event	conference - Duration: 1 Jan 2010 → …

Conference

Conference	conference
Period	01/01/10 → …

Access to Document

10.1109/ECBS.2008.39

Cite this

Lafond, S., & Lilius, J. (2008). Interrupt costs in embedded system with short latency hardware accelerators. In Bustard, W. David, Sterritt, & Roy (Eds.), 15th Annual IEEE International Conference and Workshop on the Engineering of Computer Based Systems, Proceedings (pp. 317–325). International conference and workshops on engineering of computer-based systems. https://doi.org/10.1109/ECBS.2008.39

Lafond, Sebastien ; Lilius, Johan. / Interrupt costs in embedded system with short latency hardware accelerators. 15th Annual IEEE International Conference and Workshop on the Engineering of Computer Based Systems, Proceedings. editor / Bustard ; W. David ; Sterritt ; Roy. International conference and workshops on engineering of computer-based systems, 2008. pp. 317–325

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Lafond, S & Lilius, J 2008, Interrupt costs in embedded system with short latency hardware accelerators. in Bustard, W David, Sterritt & Roy (eds), 15th Annual IEEE International Conference and Workshop on the Engineering of Computer Based Systems, Proceedings. International conference and workshops on engineering of computer-based systems, pp. 317–325, conference, 01/01/10. https://doi.org/10.1109/ECBS.2008.39

Interrupt costs in embedded system with short latency hardware accelerators. / Lafond, Sebastien ; Lilius, Johan.
15th Annual IEEE International Conference and Workshop on the Engineering of Computer Based Systems, Proceedings. ed. / Bustard; W. David; Sterritt; Roy. International conference and workshops on engineering of computer-based systems, 2008. p. 317–325.

Research output: Chapter in Book/Conference proceeding › Published conference proceeding › Scientific › peer-review

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Lafond S , Lilius J. Interrupt costs in embedded system with short latency hardware accelerators. In Bustard, David W, Sterritt, Roy, editors, 15th Annual IEEE International Conference and Workshop on the Engineering of Computer Based Systems, Proceedings. International conference and workshops on engineering of computer-based systems. 2008. p. 317–325 doi: 10.1109/ECBS.2008.39