Interrupt costs in embedded system with short latency hardware accelerators

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    This paper presents a methodology for analyzing the impact of short latency hardware accelerators on a typical embedded system. We show that hardware accelerator granularity has a direct effect on the system performance in terms of cache misses, execution time and thus energy consumption.
    Original languageUndefined/Unknown
    Title of host publication15th Annual IEEE International Conference and Workshop on the Engineering of Computer Based Systems, Proceedings
    Editors Bustard, W. David, Sterritt, Roy
    PublisherInternational conference and workshops on engineering of computer-based systems
    Number of pages9
    ISBN (Print)978-0-7695-3141-0
    Publication statusPublished - 2008
    MoE publication typeA4 Article in a conference publication
    Eventconference -
    Duration: 1 Jan 2010 → …


    Period01/01/10 → …

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