Evaluation of CPU Hotplug Latency on Multi-Core ARM Chips

Shutting down CPU cores by using sleep states is the currently used technique for reducing the ever increasing static power in microprocessors. The CPU sleep states allows power gating of the CPU and its internal logic, and the wake-up is achieved only with a physical intercore interrupt signal. Shutting down core does not only pose a problem to the mapping question, but a significantly large latency in shutdown/wake-up sequences prohibits power managers from making effective decisions for programs with a time granularity finer than the latency itself. In this work, we provide insights into the sleep state mechanism and present the practical time granularity limit in power managers for using sleep states on two recent ARM based platforms.