TY - GEN
T1 - Energy Efficiency Platform Characterization for Heterogeneous Multicore Architectures
AU - Rexha, Hergys
AU - Lafond, Sebastien
PY - 2019
Y1 - 2019
N2 - Runtime estimation of power dissipation and performance is crucial in every computing platform. In mobile systems,a special focus is set on energy efficiency in order to achievethe longest possible battery life and at the same time adheringto performance requirements. Powered by heterogeneous SoC’s,mobile systems are called to reach an energy efficient state ofexecution, with a runtime system or scheduler that requiresknowledge on the current performance and power dissipation.Today, highly heterogeneous architectures provide many actuators to reach better efficiency, the effect of which is usuallyunknown at runtime. In this paper, we propose a fast approach tobuild an energy efficiency model based on hardware performancecounters. Our approach obviates the need for power sensorspresent at the chip level and deals with high numbers of executionmodes. In building the energy efficiency model we account forthe change in temperature which, as we show, has an impacton the optimal energy efficiency choice. The proposed approachreduces significantly the time to characterize the energy efficiencyof a Multiprocessor System-on-Chip (MPSoC) and includes theenvironment temperature as a variable in determining the energyefficiency
AB - Runtime estimation of power dissipation and performance is crucial in every computing platform. In mobile systems,a special focus is set on energy efficiency in order to achievethe longest possible battery life and at the same time adheringto performance requirements. Powered by heterogeneous SoC’s,mobile systems are called to reach an energy efficient state ofexecution, with a runtime system or scheduler that requiresknowledge on the current performance and power dissipation.Today, highly heterogeneous architectures provide many actuators to reach better efficiency, the effect of which is usuallyunknown at runtime. In this paper, we propose a fast approach tobuild an energy efficiency model based on hardware performancecounters. Our approach obviates the need for power sensorspresent at the chip level and deals with high numbers of executionmodes. In building the energy efficiency model we account forthe change in temperature which, as we show, has an impacton the optimal energy efficiency choice. The proposed approachreduces significantly the time to characterize the energy efficiencyof a Multiprocessor System-on-Chip (MPSoC) and includes theenvironment temperature as a variable in determining the energyefficiency
KW - Energy Efficiency Models
KW - MPSoC
KW - Platform Configuration Point
KW - Energy Efficiency Models
KW - MPSoC
KW - Platform Configuration Point
KW - Energy Efficiency Models
KW - MPSoC
KW - Platform Configuration Point
M3 - Konferensbidrag
T3 - CEUR-WS.org
SP - –
BT - Proceedings of the 6th International Conference on ICT for Sustainability
A2 - Wolff, Annika
T2 - ICT4S 2019 ICT for Sustainability
Y2 - 10 June 2019 through 14 June 2019
ER -