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Heterogeneous architectures offer the opportunity to achieve high performance and energy efficiency by selecting appropriate cores for the execution of ever-changing software applications. Appropriate core selection depends on the interaction between the structural properties of the software and the hardware that influences the performance of the software. We propose a model for efficient core selection when executing software on ARM's big.LITTLE heterogeneous architecture. It features a metric based on the correlation between the performance and the number of last-level data cache (LLC) misses on a big and a LITTLE core. Additionally, our model defines a soft threshold in terms of the number of LLC misses, which determines efficient core selection. We verify the model using stress and variable workload benchmarks as well as two popular high-throughput applications for mutlicore targets, namely, HEVC and LDPC decoders, profiled with X-Mem, Linux perf, and PMCTrack dynamic tools. Results show that our model can be used for efficient core selection with a relatively small error probability.
|Journal||Concurrency and Computation: Practice and Experience|
|Publication status||Published - 2019|
|MoE publication type||A1 Journal article-refereed|
- ARM big.LITTLE architecture
- cycles per instruction
- last level data cache misses