Thermal modelling of 3D multicore systems in a flip-chip package

A4 Conference proceedings

Internal Authors/Editors

Publication Details

List of Authors: Kameswar Rao Vaddina, Tamoghna Mitra, Pasi Liljeberg, Juha Plosila
Editors: Thomas Büchner
Place: Piscataway, NJ
Publication year: 2010
Publisher: IEEE
Book title: SOC Conference (SOCC), 2010 IEEE International
Start page: 379
End page: 383
ISBN: 978-1-4244-6682-5


Three-dimensional (3D) technology offers greater device integration, reduced signal delay and reduced interconnect power. It also provides greater design flexibility by allowing heterogeneous integration. In this work, a 3D thermal model of a multicore system is developed to investigate the effects of hotspot, and placement of silicon die layers, on the thermal performance of a modern flip-chip package. In this regard, both the steady-state and transient heat transfer analysis has been performed on the 3D flip-chip package. Two different thermal models were evaluated under different operating conditions. Through experimental simulations, we have found a model which has better thermal performance. The optimal placement solution is also provided based on the maximum temperature attained by the individual silicon dies. We have also provided the improvement that is required in the heat sink thermal resistance of a 3D system when compared to the single-die system.

Last updated on 2019-21-09 at 03:42