Parallel Decoder for Low Density Parity Check Codes: A MPSoC Study

A4 Conference proceedings


Internal Authors/Editors


Publication Details

List of Authors: Sudeep Kanur, Georgios Georgakarakos, Antti Siirilä, Jérémie Lagravière, Kristian Nybom, Sébastien Lafond, Johan Lilius
Editors: Smari WW, Zeljkovic V
Publication year: 2013
Publisher: IEEE
Book title: High Performance Computing and Simulation (HPCS), 2013 International Conference on
Start page: 202
End page: 206
ISBN: 978-1-4799-0836-3


Abstract

The near channel performance of Low Density Parity Check Codes (LDPC) has motivated its wide applications. Itera- tive decoding of LDPC codes provides significant implementation challenges as the complexity grows with the code size. Recent trends in integrating Multiprocessor System on Chip (MPSoC) with Network on Chip (NoC) gives a modular platform for parallel implementation. This paper presents an implementation platform for decoding LDPC codes based on HeMPS, an open source MPSoC framework based on NoC communication fabric. Reduced minimum sum algorithm is used for decoding LDPC codes and simulations are performed using HeMPS tool. The data rate and speedup factor measured for decoding a rate 1/2 LDPC code characterised by 252 × 504 parity matrix is presented.

Last updated on 2019-20-08 at 07:51