Efficient GPU and CPU-based LDPC decoders for long codewords

A1 Journal article (refereed)


Internal Authors/Editors


Publication Details

List of Authors: Gronroos S, Nybom K, Bjorkqvist J
Publisher: SPRINGER
Publication year: 2012
Journal: Analog Integrated Circuits and Signal Processing
Journal acronym: ANALOG INTEGR CIRC S
Volume number: 73
Start page: 583
End page: 595
Number of pages: 13
ISSN: 0925-1030


Abstract

The next generation DVB-T2, DVB-S2, and DVB-C2 standards for digital television broadcasting specify the use of low-density parity-check (LDPC) codes with codeword lengths of up to 64800 bits. The real-time decoding of these codes on general purpose computing hardware is useful for completely software defined receivers, as well as for testing and simulation purposes. Modern graphics processing units (GPUs) are capable of massively parallel computation, and can in some cases, given carefully designed algorithms, outperform general purpose CPUs (central processing units) by an order of magnitude or more. The main problem in decoding LDPC codes on GPU hardware is that LDPC decoding generates irregular memory accesses, which tend to carry heavy performance penalties (in terms of efficiency) on GPUs. Memory accesses can be efficiently parallelized by decoding several codewords in parallel, as well as by using appropriate data structures. In this article we present the algorithms and data structures used to make log-domain decoding of the long LDPC codes specified by the DVB-T2 standard-at the high data rates required for television broadcasting-possible on a modern GPU. Furthermore, we also describe a similar decoder implemented on a general purpose CPU, and show that high performance LDPC decoders are also possible on modern multi-core CPUs.


Keywords

CUDA, DVB-T2, LDPC, SDR, SIMD, SSE

Last updated on 2019-19-11 at 03:39