Generation of Structural VHDL Code with Library Components from Formal Event-B Models

D4 Published development or research report or study


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Publication Details

List of Authors: Sergey Ostroumov, Leonidas Tsiopoulos, Juha Plosila, Kaisa Sere
Publisher: Turku Centre for Computer Science (TUCS)
Place: Turku
Publication year: 2013
Start page: 1
End page: 25
ISBN: 978-952-12-2869-8


Abstract

We propose a design approach to integrating correct-by-construction formal modeling with hardware implementations in VHDL. Formal modeling is performed within the Event-B framework that supports the refinement approach, i.e., stepwise unfolding of system properties in a correct-by-construction manner. After an implementable deterministic model of a hardware system is derived, we apply an additional refinement step in order to introduce hardware library components in the form of functions. We show the mapping between these functions and corresponding library components such that a structural, i.e., component-based, VHDL description is derived. The application of functions binds unrestricted data types and substitutes regular operations with function calls. The approach is presented through examples that illustrate the additional refinement step and the code generation. We show the advantages in terms of occupied area and performance of the descriptions that incorporate hardware library components. In addition, we show generation of test cases from a formal model, which facilitates conformance or online testing.

Last updated on 2019-15-10 at 02:47

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