Energy Efficiency Platform Characterization for Heterogeneous Multicore Architectures

A4 Conference proceedings

Internal Authors/Editors

Publication Details

List of Authors: Hergys Rexha, Sebastien Lafond
Editors: Annika Wolff
Publication year: 2019
Journal: CEUR Workshop Proceedings
Book title: Proceedings of the 6th International Conference on ICT for Sustainability
Volume number: 2382
ISSN: 1613-0073


Runtime estimation of power dissipation and performance is crucial in every computing platform. In mobile systems,
a special focus is set on energy efficiency in order to achieve
the longest possible battery life and at the same time adhering
to performance requirements. Powered by heterogeneous SoC’s,
mobile systems are called to reach an energy efficient state of
execution, with a runtime system or scheduler that requires
knowledge on the current performance and power dissipation.
Today, highly heterogeneous architectures provide many actuators to reach better efficiency, the effect of which is usually
unknown at runtime. In this paper, we propose a fast approach to
build an energy efficiency model based on hardware performance
counters. Our approach obviates the need for power sensors
present at the chip level and deals with high numbers of execution
modes. In building the energy efficiency model we account for
the change in temperature which, as we show, has an impact
on the optimal energy efficiency choice. The proposed approach
reduces significantly the time to characterize the energy efficiency
of a Multiprocessor System-on-Chip (MPSoC) and includes the
environment temperature as a variable in determining the energy


Energy Efficiency Models, MPSoC, Platform Configuration Point


Last updated on 2020-31-03 at 08:21