Interrupt costs in embedded system with short latency hardware accelerators

A4 Conference proceedings


Internal Authors/Editors


Publication Details

List of Authors: Lafond S, Lilius J
Editors: Bustard, David W. and Sterritt, Roy
Publication year: 2008
Publisher: International conference and workshops on engineering of computer-based systems
Book title: 15th Annual IEEE International Conference and Workshop on the Engineering of Computer Based Systems, Proceedings
Start page: 317
End page: 325
Number of pages: 9
ISBN: 978-0-7695-3141-0


Abstract

This paper presents a methodology for analyzing the impact of short latency hardware accelerators on a typical embedded system. We show that hardware accelerator granularity has a direct effect on the system performance in terms of cache misses, execution time and thus energy consumption.

Last updated on 2019-17-08 at 05:37