Exploring Energy Efficiency Model Generalization on Multicore Embedded Platforms

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Publication Details

List of Authors: Hergys Rexha, Sébastien Lafond
Publication year: 2018
Publisher: IEEE
Book title: 26th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP)
Start page: 494
End page: 498
Number of pages: 5
ISBN: 978-1-5386-4976-3
eISBN: 978-1-5386-4975-6


In this paper we investigate the relation between energy efficiency model and workload type executed in modern embedded architectures. From the energy efficiency model obtained in our previous work we select a few configuration points to verify that the prediction in terms of relative energy efficiency is maintained through different workload scenarios. A configuration point is defined as a set of platform tunable metrics, such as DVFS point, DPM level and utilization rate. As workloads, we use a combination of synthetic generators and real world applications from the embedded domain. In our experiments we use two different architectures for testing the model generality, which provide examples of real systems. First we have a comparison of the efficiency obtained by the two architecturally different chips (ARM and INTEL) in different configuration points and different workload scenarios. Second we try to explain the different results through the thermal management done by the two different chips. At the end we show that only in the case of workloads highly composed by integer instructions the results from the two architectures converge and show the need for a specific model trained with integer operations.


Last updated on 2019-19-05 at 03:50