Interrupt costs in embedded system with short latency hardware accelerators

A4 Konferenspublikationer


Interna författare/redaktörer


Publikationens författare: Lafond S, Lilius J
Redaktörer: Bustard, David W. and Sterritt, Roy
Publiceringsår: 2008
Förläggare: International conference and workshops on engineering of computer-based systems
Moderpublikationens namn: 15th Annual IEEE International Conference and Workshop on the Engineering of Computer Based Systems, Proceedings
Artikelns första sida, sidnummer: 317
Artikelns sista sida, sidnummer: 325
Antal sidor: 9
ISBN: 978-0-7695-3141-0


Abstrakt

This paper presents a methodology for analyzing the impact of short latency hardware accelerators on a typical embedded system. We show that hardware accelerator granularity has a direct effect on the system performance in terms of cache misses, execution time and thus energy consumption.

Senast uppdaterad 2020-04-04 vid 07:09